View CY7C1364CV33-166AXC_8454051.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c1364cv33 9-mbit (256 k 32) pipelined sync sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-74576 rev. *b revised november 1, 2012 9-mbit (256 k 32) pipelined sync sram features registered inputs and outputs for pipelined operation 256 k 32 common i/o architecture 3.3 v core power supply (v dd ) 2.5 v/3.3 v i/o power supply (v ddq ) fast clock-to-output times ? 3.5 ns (for 166-mhz device) provide high-performance 3-1-1-1 access rate user-selectable burst counter supporting intel ? ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed writes asynchronous output enable available in jedec-standard lead-free 100-pin tqfp package tqfp available with 3-chip enable ?zz? sleep mode option functional description the cy7c1364cv33 sram integrates 256 k 32 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw [a:d] , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycl e.this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to four bytes wide as controlled by the byte write control inputs. gw when active low causes all bytes to be written. the cy7c1364cv33 operates from a +3.3 v core power supply while all outputs may operate with either a +2.5 or +3.3 v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide description 166 mhz unit maximum access time 3.5 ns maximum operating current 180 ma maximum cmos standby current 40 ma
cy7c1364cv33 document number: 001-74576 rev. *b page 2 of 21 logic block diagram ? cy7c1364cv33 address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a0, a1, a bw b bw c bw d bw a memory array dqs sleep control zz a [1:0] 2 dq a byte write register dq b byte write register dq c byte write register dq d byte write register dq a byte write driver dq b byte write driver dq c byte write driver dq d byte write driver
cy7c1364cv33 document number: 001-74576 rev. *b page 3 of 21 contents pin configurations ........................................................... 4 pin definitions .................................................................. 5 functional overview ........................................................ 6 single read accesses ................................................ 6 single write accesse s initiated by adsp ................... 6 single write accesses initiate d by adsc ................... 6 burst sequences ......................................................... 7 sleep mode ................................................................. 7 interleaved burst address tabl e ................................. 7 linear burst address table ......................................... 7 zz mode electrical characteri stics .............................. 7 truth table ........................................................................ 8 truth table for read/write .............................................. 9 maximum ratings ........................................................... 10 operating range ............................................................. 10 electrical characteristics ............................................... 10 capacitance .................................................................... 11 thermal resistance ........................................................ 11 ac test loads and waveforms ..................................... 11 switching characteristics .............................................. 12 switching waveforms .................................................... 13 ordering information ...................................................... 17 ordering code definitions ..... .................................... 17 package diagram ............................................................ 18 acronyms ........................................................................ 19 document conventions ................................................. 19 units of measure ....................................................... 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 21 worldwide sales and design s upport ......... .............. 21 products .................................................................... 21 psoc solutions ......................................................... 21
cy7c1364cv33 document number: 001-74576 rev. *b page 4 of 21 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout (3 chip enable) (a version) a a a a a 1 a 0 nc nc v ss v dd nc a a a a a a a a nc dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a nc nc dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d nc a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode byte a byte b byte d byte c cy7c1364cv33
cy7c1364cv33 document number: 001-74576 rev. *b page 5 of 21 pin definitions name 100-pin tqfp i/o description a 0 , a 1 , a 37, 36, 32, 33, 34, 35, 43, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 input- synchronous address inputs used to select one of the 256k address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1:a0 feed the 2-bit counter. bw a , bw b , bw c , bw d 93, 94, 95, 96 input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw 88 input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw [a:d] and bwe ). bwe 87 input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk 89 input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 98 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 97 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 92 (for 3 chip enable version) input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device.ce 3 is assumed active throughout this document for bga. ce 3 is sampled only when a new external address is loaded. oe 86 input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as ou tputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the firs t clock of a read cycle when emerging from a deselected state. adv 83 input- synchronous advance input signal, sampled on the rising edge of clk , active low . when asserted, it automatica lly increments the add ress in a burst cycle. adsp 84 input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, a is captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc 85 input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, a is captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz 64 input- asynchronous zz ?sleep? input, active high . this input, when high places the device in a non-time-critical ?sleep? cond ition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outp uts, they deliver the data contained in the memory location specif ied by ?a? during the previous cl ock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq are placed in a tri-state condition. v dd 15, 41, 65, 91 power supply power supply inputs to the core of the device . v ss 17, 40, 67, 90 ground ground for the core of the device .
cy7c1364cv33 document number: 001-74576 rev. *b page 6 of 21 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. the cy7c1364cv33 su pports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the pr ocessor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burs t counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw [a:d] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address advancement logic and the address register while being presented to the memory array. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within t co if oe is active low. the only exception occurs when the sram is emer ging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutiv e single read cycles are supported. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will tri-state immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the ram array. the write signals (gw , bwe , and bw [a:d] ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dq inputs is written into the corresponding address location in the memory array. if gw is high, then the write operation is controlled by bwe and bw [a:d] signals. the cy7c1364cv33 provides byte write capability that is described in the write cycle descriptions ta ble. asserting the byte write enable input (bwe ) with the selected byte write (bw [a:d] ) input, will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1364cv33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. doing so will tri-state the output drivers. as a safety precaution, dq are automatically tr i-stated whenever a write cycle is detected, re gardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw [a:d] ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address pres ented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dq is written into the corresponding address location in the memory core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. v ddq 4, 11, 20, 27, 54, 61, 70, 77 i/o power supply power supply for the i/o circuitry . v ssq 5, 10, 21, 26, 55, 60, 71, 76 i/o ground ground for the i/o circuitry . mode 31 input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. nc 1, 14, 16, 30, 38, 39, 42, 51, 66, 80 no connects . not internally connected to the die. pin definitions (continued) name 100-pin tqfp i/o description
cy7c1364cv33 document number: 001-74576 rev. *b page 7 of 21 because the cy7c1364cv33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. doing so will tri-state the output drivers. as a safety precaution, dqs are automatically tri-stated whenever a write cycle is detected , regardless of the state of oe . burst sequences the cy7c1364cv33 provides a two-bit wraparound counter, fed by a1:a0, that implements eit her an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to s upport processors that follow a linear burst sequence. the burs t sequence is user selectable through the mode input. asserting adv low at clock rise will au tomatically increment the burst counter to the next addre ss in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the o peration guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low . interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 50 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current t his parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ? ns
cy7c1364cv33 document number: 001-74576 rev. *b page 8 of 21 truth table the truth table for cy7c1364cv33 follows. [1, 2, 3, 4, 5, 6] next cycle address used zz ce 3 ce 2 ce 1 adsp adsc adv oe dq write unselected none l x x h x l x x tri-state x unselected none l h x l l x x x tri-state x unselected none l x l l l x x x tri-state x unselected none l h x l h l x x tri-state x unselected none l x l l h l x x tri-state x begin read external l l h l l x x x tri-state x begin read external l l h l h l x x tri-state read continue read next l x x x h h l h tri-state read continue read next l x x x h h l l dq read continue read next l x x h x h l h tri-state read continue read next l x x h x h l l dq read suspend read current l x x x h h h h tri-state read suspend read current l x x x h h h l dq read suspend read current l x x h x h h h tri-state read suspend read current l x x h x h h l dq read begin write current l x x x h h h x tri-state write begin write current l x x h x h h x tri-state write begin write external l l h l h h x x tri-state write continue write next l x x x h h h x tri-state write continue write next l x x h x h h x tri-state write suspend write current l x x x h h h x tri-state write suspend write current l x x h x h h x tri-state write zz ?sleep? none h x x x x x x x tri-state x notes 1. x = ?don't care.? h = logic high, l = logic low. 2. write = l when any one or more byte write enable signals (bw a , bw b , bw c , bw d ) and bwe = l or gw = l. write = h when all byte write enable signals (bw a , bw b , bw c , bw d ), bwe , gw = h . 3. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 4. ce 1 , ce 2 , and ce 3 are available only in the tqfp package. 5. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw [a:d] . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 6. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low).
cy7c1364cv33 document number: 001-74576 rev. *b page 9 of 21 truth table for read/write the truth table for read/write for cy7c1364cv33 follows. [7, 8] function gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a ? dq a hlhhhl write byte b ? dq b hlhhlh write bytes b, a h l h h l l write byte c ? dq c hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? dq d hllhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b h l l l l h write all bytes h l l l l l write all bytes l x x x x x notes 7. x = ?don't care.? h = logic high, l = logic low. 8. write = l when any one or more byte write enable signals (bw a , bw b , bw c , bw d ) and bwe = l or gw = l. write = h when all byte write enable signals (bw a , bw b , bw c , bw d ), bwe , gw = h .
cy7c1364cv33 document number: 001-74576 rev. *b page 10 of 21 maximum ratings exceeding maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 ? c to +150 ?? c ambient temperature with power applied ... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v dd relative to gnd .....?0.5 v to +4.6 v supply voltage on v ddq relative to gnd .... ?0.5 v to +v dd dc voltage applied to outputs in tri-state ..........................................?0.5 v to v ddq + 0.5 v dc input voltage ................................ ?0.5 v to v dd + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............. >2001 v latch-up current ..................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / +10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range parameter [9, 10] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [8] for 3.3 v i/o 2.0 v dd + 0.3 v v for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [8] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ? 5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ? 30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 6-ns cycle, 166 mhz ? 180 ma i sb1 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc 6-ns cycle, 166 mhz ? 110 ma i sb2 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = 0 6-ns cycle, 166 mhz ? 40 ma notes 9. overshoot: v ih(ac) < v dd +1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 10. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1364cv33 document number: 001-74576 rev. *b page 11 of 21 i sb3 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc 6-ns cycle, 166 mhz ? 100 ma i sb4 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 6-ns cycle, 166 mhz ? 40 ma electrical characteristics (continued) over the operating range parameter [9, 10] description test conditions min max unit capacitance parameter [11] description test conditions 100-pin tqfp max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 5 pf c clk clock input capacitance 5pf c i/o input/output capacitance 5pf thermal resistance parameter [11] description test conditions 100-pin tqfp package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 29.41 ? c/w ? jc thermal resistance (junction to case) 6.13 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3v i/o test load 2.5v i/o test load note 11. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1364cv33 document number: 001-74576 rev. *b page 12 of 21 switching characteristics over the operating range parameter [12, 13] description -166 unit min max t power v dd (typical) to the first access [14] 1? ms clock t cyc clock cycle time 6.0 ? ns t ch clock high 2.4 ? ns t cl clock low 2.4 ? ns output times t co data output valid after clk rise ? 3.5 ns t doh data output hold after clk rise 1.25 ? ns t clz clock to low z [15, 16, 17] 1.25 ? ns t chz clock to high z [15, 16, 17] 1.25 3.5 ns t oev oe low to output valid ? 3.5 ns t oelz oe low to output low z [15, 16, 17] 0 ? ns t oehz oe high to output high z [15, 16, 17] ? 3.5 ns set-up times t as address set-up before clk rise 1.5 ? ns t ads adsc , adsp set-up before clk rise 1.5 ? ns t advs adv set-up before clk rise 1.5 ? ns t wes gw , bwe , bw [a:d] set-up before clk rise 1.5 ? ns t ds data input set-up before clk rise 1.5 ? ns t ces chip enable set-up before clk rise 1.5 ? ns hold times t ah address hold after clk rise 0.5 ? ns t adh adsp , adsc hold after clk rise 0.5 ? ns t advh adv hold after clk rise 0.5 ? ns t weh gw , bwe , bw [a:d] hold after clk rise 0.5 ? ns t dh data input hold after clk rise 0.5 ? ns t ceh chip enable hold after clk rise 0.5 ? ns notes 12. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 13. test conditions shown in (a) of figure 2 on page 11 unless otherwise noted. 14. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 15. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 2 on page 11 . transition is measured 200 mv from steady-state voltage. 16. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user condi tions. device is designed to achieve high-z prior to low-z under the same system conditions. 17. this parameter is sampled and not 100% tested.
cy7c1364cv33 document number: 001-74576 rev. *b page 13 of 21 switching waveforms figure 3. read cycle timing [18] t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bw[a:d] data out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address don?t care undefined note 18. on this diagram, when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high.
cy7c1364cv33 document number: 001-74576 rev. *b page 14 of 21 figure 4. write cycle timing [19, 20] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw[a :d] data out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined note 19. full width write can be initiated by either gw low; or by gw high, bwe low and bw [a:d] low. 20. the data bus (q) remains in high z following a write cycle unless an adsp , adsc , or adv cycle is performed.
cy7c1364cv33 document number: 001-74576 rev. *b page 15 of 21 figure 5. read/write cycle timing [21, 22, 23] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw[a:d] data out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 don?t care undefined a3 notes 21. on this diagram, when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 22. the data bus (q) remains in high z following a write cycle unless an adsp , adsc , or adv cycle is performed. 23. gw is high.
cy7c1364cv33 document number: 001-74576 rev. *b page 16 of 21 figure 6. zz mode timing [24, 25] switching waveforms (continued) t zz i supply clk zz t zzrec all inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 24. device must be deselected when entering zz mode. see cycle de scriptions table for all possible signal conditions to deselect the device. 25. dqs are in high z when exiting zz sleep mode.
cy7c1364cv33 document number: 001-74576 rev. *b page 17 of 21 ordering code definitions ordering information not all of the speed, package and temperature ranges are availa ble. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range 166 CY7C1364CV33-166AXC 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free (3 chip enable) commercial temperature range: c = commercial = 0 c to +70 c x = pb-free package type: a = 100-pin tqfp speed grade: 166 mhz v33 = 3.3 v v dd process technology: c ? 90 nm part identifier: 1364 = dcd, 256 k 32 (9 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c 1364 c - 166 c a v33 x cy 7
cy7c1364cv33 document number: 001-74576 rev. *b page 18 of 21 package diagram figure 7. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1364cv33 document number: 001-74576 rev. *b page 19 of 21 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal-oxide-semiconductor eia electronic industries alliance i/o input/output jedec joint electron devices engineering council oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1364cv33 document number: 001-74576 rev. *b page 20 of 21 document history page document title: cy7c1364cv33, 9-mbit (256 k 32) pipelined sync sram document number: 001-74576 rev. ecn no. issue date orig. of change description of change ** 3463127 12/13/2011 prit new data sheet *a 3507671 01/24/2012 prit changed stat us from preliminary to final. *b 3800190 11/01/2012 prit no technical updates. completing sunset review.
document number: 001-74576 rev. *b revised november 1, 2012 page 21 of 21 i486 is a trademark, and intel and pentium are registered trademarks, of intel corporation. powerpc is a registered trademark o f ibm corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1364cv33 ? cypress semiconductor corporation, 2011-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY7C1364CV33-166AXC

	To Download CY7C1364CV33-166AXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .